In recent years, there is an increasing demand for system large scale integration (LSI) circuits to implement secure information represented by an encryption key. The memory capacity needed for such a purpose usually ranges from approximately several kilobits to approximately several hundreds of kilobits, and the memory does not require a very large capacity. However, information leakage due to analysis needs to be prevented. In order to prevent information leakage due to analysis, a method in which written information is not read from, e.g., layout and tracks of written information, such as a method in which a nonvolatile memory, such as a flash memory, is used, is useful.
When a nonvolatile memory, such as a flash memory, is incorporated into a system LSI circuit, a special process step needs to be added to a standard complementary metal oxide semiconductor (CMOS) process, resulting in complication of the process and an increase in cost. Here, in particular, when the necessary memory capacity is small, a need exists for inexpensive nonvolatile memories which can be mounted on the system LSI circuit without adding a special process step to the standard CMOS process.
As a technique related to this need, a nonvolatile semiconductor memory device has been proposed which includes an n-channel field effect transistor (hereinafter abbreviated as NMOSFET (metal oxide semiconductor field effect transistor)) and a PMOS capacitor.
The structure and operation of such a nonvolatile semiconductor memory device will be described hereinafter with reference to the drawings (see, for example, Japanese Patent Publication No. H06-334190 (hereinafter referred to as Document 1)).
FIG. 9 is a cross-sectional view of a nonvolatile semiconductor memory device 100 described in Document 1.
The nonvolatile semiconductor memory device 100 is formed on a p-type silicon substrate 101, and includes an NMOSFET 120 serving as a read transistor, and a PMOS capacitor 121 formed on an n-type well 105 formed in the p-type silicon substrate 101. The NMOSFET 120 includes a polysilicon gate electrode 103 formed on the p-type silicon substrate 101 with a gate insulating film 104 interposed therebetween, and source/drain impurity layers 102a and 102b formed in portions of the p-type silicon substrate 101 located at both sides of the polysilicon gate electrode 103. The PMOS capacitor 121 is formed on the n-type well 105, and includes p-type impurity layers 106a and 106b serving as electrodes of the capacitor, a polysilicon gate electrode 108 formed on the n-type well 105 with a gate insulating film 109 interposed therebetween, and an n-well contact impurity layer 107.
Here, the polysilicon gate electrode 103 and the polysilicon gate electrode 108 form portions of a continuous polysilicon layer, and a floating gate 110 is formed by connecting the polysilicon gate electrode 103 and the polysilicon gate electrode 108 together. The source/drain impurity layers 102a and 102b are connected to terminals 112 and 111, respectively. The p-type impurity layers 106a and 106b and the n-well contact impurity layer 107 are connected through a metal interconnect to a terminal 113, and have the same potential.
Next, operations of the nonvolatile semiconductor memory device 100 will be described with reference to FIGS. 10A-10C.
First, a write operation will be described with reference to FIG. 10A. In the write operation, the p-type silicon substrate 101 and the terminals 111 and 112 are all at ground potential, and a high positive voltage is applied to the terminal 113. This allows the floating gate 110 to have a positive potential relative to the ground potential by capacitive coupling, and a tunneling current flows through the gate insulating film 104 under the polysilicon gate electrode 103, resulting in injection of electrons into the polysilicon gate electrode 103, i.e., the floating gate 110. In this manner, the write operation is performed.
Next, a read operation will be described with reference to FIG. 10B. In the read operation, the p-type silicon substrate 101 and the terminal 111 are at ground potential, and, for example, a read voltage of approximately +3 V is applied to the terminals 112 and 113. Here, when electrons have not been injected into the floating gate 110, positive charge is generated in the polysilicon gate electrode 103, and a conduction channel is formed between the source/drain impurity layers 102a and 102b, thereby allowing a read current to flow through the terminal 112. In contrast, when electrons have been injected into the floating gate 110, the voltage of the polysilicon gate electrode 103 is not sufficiently positive, and thus, a read current does not flow through the terminal 112. In this manner, the read operation can be performed.
Next, an erase operation will be described with reference to FIG. 10C. In the erase operation, the terminal 113 is at ground potential, and a high positive voltage is applied to the terminals 111 and 112. Thus, a voltage is applied between the floating gate 110 in which electrons are stored and the source/drain impurity layers 102a and 102b, thereby allowing a tunneling current to flow through portions of the gate insulating film 104 overlapping the source/drain impurity layers 102a and 102b. As a result, electrons are removed from the floating gate 110, thereby performing the erase operation.
As above, the nonvolatile semiconductor memory device 100 operates as a floating gate memory using the n-type well 105 as a control gate.